The current trend in semiconductor manufacturing is to fabricate integrated circuit (IC) chips having reduced sizes. As such, the functional circuits containing such IC chips continue to increase in complexity. This increases the opportunity for defective chips resulting from a failed element or a defective conductor. One solution for this problem is to provide redundant circuits or redundant elements on the IC chips. For example, if a primary circuit or element becomes defective, a redundant circuit or element can be used to substitute for that defective circuit or element, which involves logic de-activation of the defective circuit or element and activation of the redundant circuit or element. One major disadvantage of the logic de-activation approach is that the defective circuit or element are still tied to the power planes of the IC chips and continue to drain power from the IC chips after the logic de-activation, which can cause functional chips to be rejected due to violations of predetermined power specifications, especially in low power logic applications.
There is therefore a need for physically and permanently canceling the defective circuits and elements and separating them from the power planes of the IC chips.
Further, advances in IC chip manufacturing technology have allowed a continuously increasing number of functionalities to be implemented on a single IC chip, and much effort has been devoted to streamline and reduce IC chip part numbers that have proliferated due to the multitudes of various customer applications. Tremendous cost savings can be realized if a “one-chip-fits-all” model is provided for the IC chip manufacturing process, and custom-modification or “personalization” of the IC chips is carried out post-manufacturing for tailoring the functionalities of the IC chips according to the specific customer application. Currently, the custom-modification or personalization is conducted at the logic level through logic activation and de-activation of various functional circuits or elements. However, after the logic custom-modification or personalization, the un-used circuits or elements are still tied to the power planes of the IC chips and continue to drain power from the IC chips. Such un-used circuits or elements can also cause the chips to be rejected due to violations of predetermined power specifications, especially in low power logic applications.
There is therefore also a need for providing custom-modification or personalization of IC chips at the wafer level so as to completely eliminate the un-used circuits or elements, separate them from the chip power planes, and reduce the overall chip loading.
Laser fuses have been used for permanently canceling defective circuits or elements and for custom-modifying/personalizing the IC chips in low power applications, which are typically characterized by low voltage drops (approximately in the order of about 0.1V) and low duty cycle limits (approximately in the order of about 0.001%). Use of currently available laser fuses in high power applications characterized by high voltage drops (in the order of at least about 2V) and high duty cycles (approximately in the order of at least about 100%), on the other hand, have resulted in reliability failures due to fuse regrowth under high voltage and high duty cycle conditions.
It would therefore be advantageous to provide improved laser fuse structures that have high current capability and are suitable for use in high power applications.